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Hardware Penetration Testing

Hardware penetration testing across Europe: chip-level, debug-port and side-channel attacks, mapped to IEC 62443 and ETSI EN 303 645. Fixed price.

Manual, expert-ledEvidence-based findingsFree remediation retest

Hardware penetration testing treats your device the way a determined attacker with a soldering iron and a logic analyser would: prise it open, find the debug port, read the flash, and see what secrets fall out. If your product ships to customers and stores keys, credentials or firmware on the board, someone will eventually do this to it. We do it first, under NDA, and tell you what they would find before your product is in the field and out of your control.

What hardware penetration testing actually covers

Software security assumes the attacker is on the network. Hardware security assumes the attacker is holding the device, and that changes everything. Physical access defeats most software controls, so the questions become different: can the debug interface be reached, is the flash readable, does secure boot actually stop a modified image, and can a single glitch skip the check that protects everything else? We test the board, the chips and the buses, not just the code running on top.

Debug interface exposure: JTAG, SWD and UART access and lockdown testing
Flash and memory extraction: SPI, I2C and eMMC dumps, chip-off recovery
Secure boot and root of trust: signature bypass and rollback testing
Fault injection and glitching: voltage and clock attacks to skip security checks
Side-channel analysis: power and timing leakage against cryptographic operations
Bus and wireless sniffing: SPI, I2C and UART traffic, plus BLE and RF interfaces
Key and credential storage: secrets in flash, EEPROM or an unprotected secure element

How we test a physical device

Every engagement is manual and hands-on, run by an engineer who is comfortable at both the bench and the disassembler. Hardware pen testing is not a scan; it is investigation. We work through the device methodically, escalating from non-invasive observation to invasive attacks only as the scope allows.

Teardown and reconnaissance

We open the device, identify every chip from its markings and datasheets, and map the board: the main processor, the flash and EEPROM, any secure element or TPM, and the debug and test pads the manufacturer left behind. A logic analyser and an oscilloscope tell us what the buses are doing at power-on, which usually points straight at the interesting targets.

Interface and memory extraction

We probe JTAG, SWD and UART to see whether debug access was disabled in production or merely hidden. Where the flash is reachable, we dump it over SPI or I2C, or lift the chip and read it directly, then pull the firmware and any secrets out of the image. Plenty of devices we test hand over their entire firmware and hardcoded keys through a header the vendor forgot to lock.

Boot chain and fault injection

We test whether secure boot genuinely enforces signatures, whether an older vulnerable firmware can be rolled back, and whether a modified image runs. Where the device relies on a check to protect its secrets, we attempt voltage and clock glitching to skip that check at the exact moment it runs, a technique that has broken many devices whose software looked airtight.

Side-channel, wireless and reporting

If cryptography is a target, we look for power and timing side channels that leak key material. We sniff and probe any BLE or proprietary RF interface for pairing and command weaknesses. Then you get a written report within days, with photos, captured traffic and the exact bench setup for every finding, plus a live walkthrough and a free retest after you respin.

Chip-level
testing down to flash, bus and glitch attacks
100%
manual, bench-based investigation
Free
retest after you remediate

Vulnerabilities we routinely find in hardware

The same handful of mistakes show up across consumer IoT, industrial controllers and connected medical or automotive parts, because they are baked in early and rarely revisited.

Open debug interfaces

JTAG, SWD or a UART console left enabled in shipped product gives an attacker a direct route to memory, firmware and often a root shell. Disabling or authenticating these in production is one of the highest-value fixes we recommend, and one of the most commonly missed.

Readable flash and extractable secrets

Unencrypted external flash is an open book. We routinely recover full firmware, API keys, Wi-Fi credentials, private certificates and update-signing keys straight from an SPI chip. When one device’s key opens the whole fleet, a five-euro flash dump becomes a product-wide compromise.

Weak or absent secure boot

A boot chain that does not verify signatures, or verifies them but allows rollback to a vulnerable version, lets an attacker run their own firmware. We test the full chain from ROM to application and prove whether a modified image survives a reboot.

Susceptibility to fault injection

Many security decisions come down to a single comparison in code. A well-timed glitch can make the processor skip it, turning a locked device into an open one. Devices without glitch detection or redundant checks are especially exposed, and this is a class of attack that pure software review never surfaces.

Insecure buses and wireless links

Sensitive data crossing an SPI or I2C bus in the clear can be sniffed with cheap equipment. BLE and proprietary radios frequently use weak pairing, static keys or unauthenticated commands, letting an attacker within range control or impersonate the device.

Cloning and counterfeiting exposure

When firmware and provisioning secrets are recoverable, a competitor can clone your product or a counterfeiter can flood your channel with copies that carry your name and your liability. We assess how hard it would be to duplicate the device from an extracted image, and whether per-unit keying, secure provisioning and an unclonable identity would actually hold up against someone motivated to copy you.

Tamper detection and physical hardening

Enclosures that pop open without a trace, test points that stay live in production, and boards with no tamper response make every other attack easier. We check whether opening or probing the device leaves evidence, and whether critical components are shielded or potted, because physical hardening is often the cheapest control to add before the next production run.

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Want this tested on your own systems?

Free 20-minute scoping call, a fixed price with no hourly surprises, and a free retest once you fix what we find.

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Compliance and standards we align with

Hardware security is now a regulatory expectation across the EU, not just good engineering, and the standards are specific about what a device must resist.

Consumer IoT and the standards behind it

ETSI EN 303 645 sets the baseline for consumer connected products, covering no default passwords, secure storage of sensitive parameters, and protection of software integrity. The EU Radio Equipment Directive (RED) delegated act and the incoming Cyber Resilience Act make much of this mandatory for products sold in Europe. Our testing and report map directly to these controls.

Industrial and OT devices

For industrial and control-system hardware, IEC 62443 (particularly 4-1 and 4-2) defines security requirements for components and their development. We assess against the relevant component requirements and provide evidence suitable for a certification effort or a customer security review.

Cryptographic and application baselines

Where the device performs cryptography we reference established key-management and side-channel expectations, and for any companion firmware or app we bring in the relevant OWASP guidance. The report gives your hardware and firmware teams a shared, standards-based reference for each fix.

What you get from the engagement

A report an electronics team can act on, not vague warnings.

  • An executive summary for leadership, certification bodies and enterprise customers
  • A technical report with each finding scored by CVSS, photographed, and paired with the bench setup and steps to reproduce it
  • Specific remediation advice: fuse settings, interface lockdown, secure-boot and key-storage changes for the next revision
  • An attestation letter to support ETSI EN 303 645, IEC 62443 or a customer review
  • A live results walkthrough with your hardware and firmware engineers
  • A free retest on the revised board once you have remediated

Everything is delivered under NDA, and any devices, dumps and findings are handled securely and returned or destroyed on request.

Why manual, bench-level testing is the only real test

There is no scanner for a printed circuit board. Reading a flash chip, timing a glitch, or spotting a key leaking through a power trace are physical acts of investigation that need equipment, patience and someone who has done it before. A design review on paper will miss the debug pad that was never disabled and the boot check that a glitch walks straight past. We put the actual product on the bench, attack it the way a competitor or a cloning operation would, and hand you the photographed proof and the concrete change for the next spin. That is hardware security testing that means something, because the attacker you are worried about is working from the same bench, just without your permission or your interest in a quiet fix.

Pricing

Pricing depends on scope: how complex the device is, whether invasive attacks like chip-off and glitching are in scope, and how many variants you need covered. Here is the shape of a typical European engagement.

Engagement What’s included Timeline Price
Essential Single device, teardown, debug-interface and flash-extraction testing, firmware and secrets review, report and free retest 5–8 working days from €3,000
Standard Device plus its wireless interfaces and secure-boot chain, bus sniffing, non-invasive fault-injection probing, and companion firmware review 8–12 working days €4,500–€10,000
Advanced Invasive attacks: chip-off, in-depth glitching and side-channel analysis against the root of trust and cryptographic engine 12–20 working days €10,000–€25,000
Compliance add-on Mapping and attestation for ETSI EN 303 645, IEC 62443 or the Cyber Resilience Act with any tier from €900
Custom / product family Several variants or a full product line, scoped after a free call on scoping custom

Every engagement is fixed-price, quoted after a free 20-minute scoping call — no hourly surprises, and a retest is included. Get a fixed quote

FAQ

How much does hardware penetration testing cost?
Hardware penetration testing cost starts from €3,000 for a single device with debug-interface and flash-extraction testing, and rises when invasive work like chip-off, glitching or side-channel analysis is in scope. You get a fixed price after a free scoping call.
How long does a hardware pen test take?
A focused device test runs about 5–8 working days; adding wireless, secure-boot and fault-injection work pushes it to 8–12, and deep invasive attacks 12–20. Bench work takes time, and we would rather do it properly than rush a glitching setup.
Do you need physical samples of the device?
Yes, ideally two or three units, since invasive testing can damage a board and we want spares. We also value schematics, a firmware image and any debug documentation, which speed the work and lower the cost.
Do you test chip-off, glitching and side-channel attacks?
We do, where scope and samples allow. Fault injection and side-channel analysis often reveal weaknesses that no amount of software review would, so they are worth including for any device whose security rests on a hardware root of trust.
Will this help with ETSI EN 303 645 or the Cyber Resilience Act?
Yes. We map findings to ETSI EN 303 645 and IEC 62443, and to the security expectations of the EU Radio Equipment Directive and Cyber Resilience Act, and provide an attestation letter suitable for certification and customer reviews.
Can you test the wireless interfaces too?
Yes. We probe BLE and proprietary RF for weak pairing, static keys and unauthenticated commands, and sniff SPI, I2C and UART buses for data crossing the board in the clear.
What do we get that a design review would not give us?
Proof. A review predicts problems; a bench test demonstrates them on the actual product, with photos, captured data and reproduction steps, so your team knows the risk is real and exactly how to close it in the next revision.
Is everything kept confidential?
Every engagement runs under NDA. Devices, firmware dumps and findings are handled securely, shared only with the people you name, and returned or destroyed on request.

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Who needs this

Device manufacturers and IoT, industrial, automotive or connected-product teams preparing for certification, a customer security review, or launch, who need to know what an attacker holding the device in their hands can actually extract.

why safetybis

Security you can prove

The same standard on every engagement, big or small.

Evidence, not opinions

Every finding ships with a reproduction and proof of concept — no vague "maybe vulnerable".

Humans over scanners

Certified engineers find the logic flaws and chained attacks automated tools walk straight past.

Fixed price, free retest

You know the cost up front, and verifying the fix is part of the deal — not a second invoice.

500+
assessments delivered
<30min
incident first response
12k+
infections removed
98%
fixed within one retest
$ safetybis quote --service "Hardware Penetration Testing"

Ready to lock this down?

Free scoping call, fixed price, free retest. Tell us what you're running and we'll take it from there — usually within one business day.

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Tell us what you're running

Scoping is free. We reply within one business day, and under 30 minutes for active incidents.